Recent developments in fast semiconductor memories will lead to high speed signal transmission rates of, for example, up to 7 Gbit/s. These high signal transmission rates require careful design considerations with respect to the implementation of an appropriate topology and a suitable method of access to the memory chips on the memory module from a memory controller.
A loop forward and a star topology are possible solutions how to arrange memory chips on a memory module, such as a DIMM considering the connection to the memory controller. In the loop forward topology, the memory chips on the memory module are arranged in such a way that command/address/write data stream (CAwD) and read data stream (rD) are transferred separately. CAwD and rD streams are transmitted in form of signal frames which are based on a predefined transmission protocol. In contrast to other possible architectures, collisions between CAwD and rD are under normal circumstances not possible. With each command usually one of four memory chips is accessed for data processing, and in the loop forward architecture three of four memory chips have only to fulfil a simple re-drive of CAwD and rD, while in the star topology the re-drive function for CAwD and rD is carried out only in the master memory chip.
To separate CAwD signal and rD signal lanes, in a semiconductor memory system arranged in the loop forward topology and having, for example, four memory chips on the memory module this transfer is done in following manner: memory controller to the first memory chip, from the first memory chip to the second memory chip, from the second memory chip to the third memory chip, and from the third memory chip to the fourth memory chip and from there to the memory controller (only rD stream). In the star topology the memory chips on the memory module are arranged such that the memory controller is directly connected only to one memory chip, namely the master memory chip and this master memory chip is connected to a number of slave memory chips in a star fashion.
Up to now a proposal exists to transfer the rank select command signal within a protocol-based frame on the regular command and data stream. This is very inflexible, because                (a) the frame must be decoded to find out what is the rank select information, i.e., which memory chip is addressed;        (b) memory chips cannot be accessed in advance for certain set-up procedures;        (c) memory chips cannot be accessed independently from the CAwD and rD stream;        (d) memory chips have to separate between re-drive versus DRAM read/write procedure—with a protocol embedded, non-separated rank signal, this leads to a higher logical effort;        (e) power consumption increases, because for decoding of rank select information main blocks in the memory chip have to be involved, even if only a re-drive has to be performed.        
In consequence without a separated rank select signal a lot of decoding has to be performed, whether the currently accessed memory chip is really the one address for data processing. That is in ¾ of all cases this is needless, and thus with a separated rank select signal the information could be available for the decoding.
A lot of more flexibility could be achieved, if a rank select signal is not embedded in the protocol-based frame but instead is transmitted separately and connected directly from the memory controller to the memory module using separated pins for this rank select signal.
As a result there is a need to provide a solution how a separated rank select signal can be transferred from the memory controller to the memory chips and decoded and processed therein.